[doc] Update stages doc with top-level stages by martin-velay · Pull Request #597 · lowRISC/mocha

martin-velay · 2026-06-03T16:47:04Z

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martin-velay · 2026-06-03T16:47:32Z

marnovandermaas

Thank you so much for this PR. I really enjoyed the motivation sections you added. I put some of my thoughts in here, which I hope are useful.

marnovandermaas · 2026-06-05T12:35:08Z

+|---------------|-----------------|
+| TOP_DV_DOC_DRAFTED | DV document drafted covering testbench architecture, agent topology, firmware-driven stimulus model, and chip-level coverage intent. |
+| TOP_VPLAN_COMPLETED | Verification plan (`top_mocha_vplan.hjson`) complete with the metric-to-test mapping for each coverage item and milestone specified. Reviewed by designers, a peer DV engineer, firmware author, and chip architect. |
+| TOP_TESTPLAN_COMPLETED | Chip-level testplan (`chip_testplan.hjson`) complete with at least one testpoint per integrated IP. Reviewed by designers, a peer DV engineer, firmware author, and chip architect. |


Same as for vplan.

I have edited the text in my last push into:

Chip-level testplan (chip_testplan.hjson) substantively complete (>90% of intended scope) with at least one testpoint per integrated IP. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major testpoint gaps remain before DV execution begins.

Is it OK for you?

martin-velay · 2026-06-15T11:47:45Z

@marnovandermaas,

I have rebased on the main in the 1st push.
The 2nd and 3rd push address some comments. Let me know if you are happy with it? In that case could you mark the related comments as resolved?

marnovandermaas

Another few comments from my end. The main issue I still have is the VPLAN and TESTPLAN completed statements for V1 and that these are not revisited in V2 and V3.

marnovandermaas · 2026-07-15T13:24:46Z

+
+1. **Register reachability:** SW writes and reads at least one CSR, confirming correct address-map wiring through the crossbar.
+2. **One integration-unique functional path:** one transaction that exercises a path only present at the chip level. The chip's external ports relevant to the IP under test must be connected to a UVM agent or a component that actively drives or passively observes them; a port left undriven or tied off does not count as exercised. This distinguishes a chip-level smoke from an IP-level smoke.
+3. **At least one interrupt delivery** (where the IP can generate an interrupt): one full machine-mode claim/complete cycle through the PLIC, confirming IP to PLIC to CPU wiring.


This is split into separate tests usually right?

I think my last push already addressed this. WDYT?

marnovandermaas · 2026-07-15T13:27:35Z

+| **Item name** | **Description** |
+|---------------|-----------------|
+| TOP_DV_DOC_DRAFTED | DV document drafted covering testbench architecture, agent topology, firmware-driven stimulus model, and chip-level coverage intent. |
+| TOP_VPLAN_COMPLETED | Verification plan (`top_mocha_vplan.hjson`) substantively complete (>90% of intended scope) with the metric-to-test mapping for each coverage item and milestone specified. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major coverage gaps or methodological misalignments remain before DV execution begins. |


I think we can remove the multiple approvals here, since we already have that step from the overall V1 approval

I have done a re-wording of this part, I hope it's better now.

marnovandermaas · 2026-07-15T13:30:02Z

+| TOP_VPLAN_COMPLETED | Verification plan (`top_mocha_vplan.hjson`) substantively complete (>90% of intended scope) with the metric-to-test mapping for each coverage item and milestone specified. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major coverage gaps or methodological misalignments remain before DV execution begins. |
+| TOP_TESTPLAN_COMPLETED | Chip-level testplan (`chip_testplan.hjson`) substantively complete (>90% of intended scope) with at least one testpoint per integrated IP. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major testpoint gaps remain before DV execution begins. |


I know we already discussed this but I still think these are very ambitious and not sure if we can do it in our time frame. If I were to write these I would change "_COMPLETED" to "_DRAFTED". I would also remove the ">90% of intended scope". And instead of "substantively complete" make it "substantively drafted".

I have done a re-wording of this part. Although, I don't want the "DRAFTED" word, I feel it's too weak. What do you think of:

| TOP_VPLAN_REVIEWED | Verification plan (`top_mocha_vplan.hjson`) substantively complete: every planned coverage item has a metric-to-test mapping and its milestone specified, with no known major coverage gaps. Reviewed with stakeholders across DV, design and software/firmware so no perspective's coverage gaps or methodological misalignments remain before DV execution begins. The plan is expected to evolve as the design matures. | | TOP_TESTPLAN_REVIEWED | Chip-level testplan (`chip_testplan.hjson`) substantively complete: at least one testpoint per integrated IP and no known major testpoint gaps. Reviewed with stakeholders across DV, design and software/firmware so no perspective's testpoint gaps remain before DV execution begins. The plan is expected to evolve as the design matures. |

Signed-off-by: martin-velay <mvelay@lowrisc.org>

martin-velay · 2026-07-16T16:07:59Z

@marnovandermaas, I think I have addressed most of your comments. I hope you'll be satisfied. At least you've raised valid points again. Thanks!

martin-velay force-pushed the top_level_stages branch from 2d50ddb to f094b94 Compare June 4, 2026 06:20

marnovandermaas reviewed Jun 5, 2026

View reviewed changes

martin-velay force-pushed the top_level_stages branch from f094b94 to 0bf8c92 Compare June 12, 2026 15:30

martin-velay marked this pull request as ready for review June 12, 2026 15:42

martin-velay force-pushed the top_level_stages branch 3 times, most recently from 3a5f103 to 274ac44 Compare June 15, 2026 11:46

martin-velay force-pushed the top_level_stages branch from 274ac44 to 0cfecc9 Compare July 9, 2026 14:38

martin-velay requested a review from marnovandermaas July 9, 2026 14:40

martin-velay force-pushed the top_level_stages branch 3 times, most recently from 548a6df to 81cf5ee Compare July 15, 2026 06:53

marnovandermaas reviewed Jul 15, 2026

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[doc] Update stages doc with top-level stages

b2fd138

Signed-off-by: martin-velay <mvelay@lowrisc.org>

martin-velay requested a review from marnovandermaas July 16, 2026 16:06

martin-velay force-pushed the top_level_stages branch from 81cf5ee to b2fd138 Compare July 16, 2026 16:07

		\| TOP_VPLAN_COMPLETED \| Verification plan (`top_mocha_vplan.hjson`) substantively complete (>90% of intended scope) with the metric-to-test mapping for each coverage item and milestone specified. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major coverage gaps or methodological misalignments remain before DV execution begins. \|
		\| TOP_TESTPLAN_COMPLETED \| Chip-level testplan (`chip_testplan.hjson`) substantively complete (>90% of intended scope) with at least one testpoint per integrated IP. Reviewed and approved by designers, a peer DV engineer, firmware author, and chip architect. Further evolution is expected as the design matures; the review ensures no major testpoint gaps remain before DV execution begins. \|

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martin-velay commented Jun 3, 2026

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martin-velay commented Jun 15, 2026

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martin-velay commented Jul 16, 2026

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